IBM Debuts World’s First Sub-1 Nanometer Chip Technology

IBM has introduced the world’s first sub-1 nanometer chip technology, utilizing a 0.7 nm (7 angstrom) node to overcome the physical limits of traditional semiconductor scaling. The breakthrough features a "nanostack" 3D architecture that enables nearly 100 billion transistors to be packed onto a chip the size of a fingernail, doubling the density of current 2 nm technology. This advancement is expected to provide substantial leaps in performance and energy efficiency, supporting the next decade of growth for generative AI, cloud infrastructure, and advanced electronic devices.

IBM’s sub-1 nm breakthrough is centered on a new transistor architecture called "nanostack," which represents the industry’s first three-dimensional, nanosheet-based design. By vertically stacking and staggering transistors through 3D sequential integration, IBM can pack nearly 100 billion transistors onto a single chip, effectively doubling the density of its 2 nm node unveiled in 2021. Technical results indicate that this 0.7 nm technology is projected to offer up to 50 percent more performance or 70 percent greater energy efficiency than previous 2 nm chips. This design also allows for the use of varying material combinations within each stacked layer to optimize power efficiency and performance independently.

The nanostack architecture has been experimentally validated through ultra-thin dielectric bonding in CMOS integration and functional CMOS inverter operation. Furthermore, research presented at VLSI 2026 showed that the architecture provides 40 percent scaling in SRAM, a critical factor for chip designers aiming to support the high-bandwidth data demands of advanced AI workloads. This move into angstrom-level scaling—where dimensions approach the size of individual atoms—extends the semiconductor roadmap for at least another decade. IBM’s projections suggest that the first adoption of this sub-1 nm technology could reach production as early as the next five years.

Much of this research is conducted at IBM’s facility in Albany, New York, which is set to receive a High Numerical Aperture Extreme Ultraviolet (High NA EUV) lithography tool from ASML. This tool is essential for the ultra-precise circuit printing required for such small nodes. IBM is collaborating with industry partners Lam Research, Tokyo Electron (TEL), and SCREEN Semiconductor Solutions to develop the necessary High NA EUV processes. In a related move to bolster domestic manufacturing, IBM also announced the formation of Anderon, a standalone pure-play quantum foundry designed to leverage the company's semiconductor expertise for quantum wafer production.